View ADM1014_21183.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

=
Preliminary Technical Data
PAUXONA
Dual PCI Hot-PlugTM Controller ADM1014
7
AUXGA
30
3.3V Cmos Input
+3.3VAux
S G
P-CHANNEL MOSFET
31 AUXINA
Q
FAUXA
5
RESET
3.3V Cmos Output
FAULT LATCH Q
SET
AUXINA
3.3VAUX POWER-ON RESET
OVERCURRENT AND UNDERVOLTAGE COMPARATORS FOR +3.3VAUX
D
8
AUXOA
AUXINA
100A VOCSET
LOW WHEN AUXINA < 2.5V
CHANNEL A
CIRCUIT OPERATES FROM 3.3VAUX POWER SUPPLY
3V5VGA
OCSET 6
COMMON TO BOTH CHANNELS
EXTERNAL N-CHANNEL POWER MOSFETS
+5V IN +3.3V IN
CIRCUIT OPERATES FROM 3.3VAUX AND +12V POWER SUPPLY
33
CHANNEL A
OVERCURRENT AND UNDERVOLTAGE COMPARATORS FOR +5V
34
35
5VSA
RSENSE5A
5VISENA
PWRONA 3
OVERCURRENT AND UNDERVOLTAGE COMPARATORS FOR +3.3V
36
37
3VSA 3VISENA
RSENSE3A
9 12VGA
Q
RESET
S G
OVERCURRENT AND UNDERVOLTAGE COMPARATORS FOR +12V
FLTNA
FAULT LATCH
4
Q
SET
P-CHANNEL MOSFET
D
29 12VIN A
+5V OUTA
+3.3V OUTA
10 12VOA 2 -12VGA 38 -12VINA
S G
12VIN A 5V REGULATOR
GND
32
12VIN A 12V IN POWER-ON RESET LOW WHEN 12VINA < 10V
COMBINING LOGIC
COMMON TO BOTH CHANNELS
N-CHANNEL MOSFET
D
OVERCURRENT COMPARATOR FOR -12V
1
-12VOA
14 26
AUXGB AUXINB
EXTERNAL N-CHANNEL POWER MOSFETS +3.3V +5V IN IN
13 AUXOB
PAUXONB 27
25
3V5VGB
+3.3VAux
CHANNEL B
FAUXB
15
24
23
5VSB
5VISENB
RSENSE5B
( IDENTICAL TO CHANNEL A )
22
21
3VSB 3VISENB
PWRONB 17
RSENSE3B
12
28
FLTNB
12VGB 12VINB 12VOB -12VGB -12VINB
+5V OUTA
+3.3V OUTA
11
16
18 20
19 -12VOB
FUNCTIONAL BLOCK DIAGRAM
REV. PrN 1/02
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
TM
Hot Plug is a trademark of Core International, Inc.
P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com (c) Analog Devices, Inc., 2002
One Technology Way, Tel: 781/329-4700 Fax: 781/326-8703
ADM1014-SPECIFICATIONS
FEATURES Controls Two PCI Slots Controls all Four PCI Supplies, +3.3V, +5V, +12V, -12V, plus 3.3V auxiliary supply Internal MOSFET Switches for +3.3V AUX, +12V and -12V outputs Adjustable Overcurrent Protection for all Outputs Undervoltage Protection on +3.3V, +5V, +12V and +3.3V AUX Supplies Open-Drain Fault Output with Adjustable Delay Logic Control of Outputs Adjustable Soft-start APPLICATIONS Compact PCI PCI Hot-PlugTM
GENERAL DESCRIPTION
The ADM1014 operates from a +12V and +3.3V AUX supply and controls five independent supplies (+3.3V, +3.3VAUX, +5V, +12V and -12V) on two separate channels (A and B). The power switches for the +3.3VAUX, +12V and -12V supplies are integrated onto the chip, and internal current limiting is provided. For the +3.3V and +5V supplies, the device drives external, N-channel, power MOSFETs, and provides overcurrent protection by sensing the voltage drop across external current-sense resistors. The current limits for all 10 supplies are set by a single resistor to GND, connected to the OCSET pin. Undervoltage sensing is provided on the +3.3V, +5V, +12V and +3.3VAux supplies. Overcurrent sensing is provided on all supplies. In the event of an overcurrent or undervoltage fault on any of the outputs of either channel, all outputs on that channel will be turned off. Turn-on slew rate may be controlled using eight external capacitors, connected to the gate drives of all of the supplies. Logic control of the four main outputs is provided by the PWRONA and PWRONB pins. When these pins are high, the outputs are turned on, when low, the outputs are turned off. The +3.3VAUX supplies have their own control inputs, PAUXA and PAUXB.
The ADM1014 is a dual PCI voltage bus controller that allows hot-plugging of adapter cards into and out of an active or passive backplane. The device requires only four external power MOSFETs and a few discrete components for a complete power-control solution for two PCI slots.
(Specifications are for each channel, 3.3VAUX=AUXINA=3.3V, VCC = 12VIN = +12V, -12VIN = -12V, Nominal 3.3V and 5V supplies to external MOSFETs, TA = 0oC to +70oC, unless otherwise noted.)
Parameter 5V/ 3.3V SUPPLY CONTROL 5V Overcurrent Threshold 5V Overcurrent Threshold Voltage 5V Overcurrent Threshold Voltage 5V Undervoltage Trip Threshold 5V Undervoltage Fault Response Time 5V Turn-On Time (PWRON High to 5VOUT = 4.75V) 3V Overcurrent Threshold 3V Overcurrent Threshold Voltage 3V Overcurrent Threshold Voltage 3V Undervoltage Trip Threshold 3V Undervoltage Fault Response Time 3V5VG Undervoltage Enable Threshold Voltage 3V Turn-On Time (PWRON High to 3VOUT = 3.00V) 3V5VG Vout High Gate Output Charge Current Gate Turn-On Time (PWRON High to 3V5VG = 11V) Gate Turn-Off Time +12V SUPPLY CONTROL On Resistance of Internal PMOS On Resistance of Internal PMOS Overcurrent Threshold Overcurrent Threshold 12V Undervoltage Trip Threshold Undervoltage Fault Response Time Min 33 70 4.42 41 89 2.74 11.5 19 Typ 8 42 80 4.65 110 9.75 10 52 98 2.86 110 9.6 9.75 11.8 25.0 280 2 Max 50 90 4.7 160 62 108 2.9 160 29 Units A mV mV V ns ms A mV mV V ns V ms V A s s Test Conditions/Comments See Typical Application Diagram VOCSET = 0.6V VOCSET = 1.2V C3V5VG = 0.033F, C5VOUT = 2000F, RL = 1 See Typical Application Diagram OCSET = 0.6V OCSET = 1.2V
C3V5VG = 0.033F, C3VOUT = 2000F, RL = 0.43 PWRON = High, FLTN = High PWRON = High, V3V5VG = 4V C3V5VG = 0.033F,3V5VG Rising 10% to 90% C3V5VG = 0.033F, 3V5VG Falling 90% to 10% PWRON = High, ID = 0.5A, TA= TJ= 25oC PWRON = High, ID = 0.5A, TA= TJ= 70oC VOCSET = 0.6V VOCSET = 1.2V
0.6 1.25 10.25 -
0.3 0.35 0.75 1.50 10.6 110
0.35 0.5 0.9 1.8 10.8 -
A A V ns
-2-
REV. PrN 1/02
ADM1014-SPECIFICATIONS (Continued)
(Specifications are for each channel, 3.3VAUX=AUXINA=3.3V, VCC = 12VIN = +12V, -12VIN = -12V, Nominal 3.3V and 5V supplies to external MOSFETs, TA = 0oC to +70oC, unless otherwise noted.)
Parameter Gate Charge Current Turn-On Time (PWRON High to 12VG = 1V) Turn-Off Time -12V SUPPLY CONTROL On Resistance of Internal NMOS On Resistance of Internal NMOS Overcurrent Threshold Overcurrent Threshold Gate Output Charge Current Turn-On Time (PWRON High to M12VO = -10.8V) Turn-Off Time M12VIN Input Bias Current +3.3VAUX SUPPLY CONTROL On Resistance of Internal PMOS On Resistance of Internal PMOS Overcurrent Threshold Overcurrent Threshold 3.3VAUX Undervoltage Trip Threshold Undervoltage Fault Response Time Gate Charge Current Turn-On Time (PAUXON High to AUXG = 1V) Turn-Off Time 3.3VAUX Power On Reset Threshold CONTROL PINS 12VIN Supply Current AUXIN Supply Current OCSET Current Overcurrent to Fault Response Time PWRONA/B, PAUXA/B Threshold Voltage 12V Power On Enable Threshold 12V Power On Reset Threshold FAULT O/P PINS FLTA/B Output Low Voltage FLTA/B Output High Voltage FLTA/B, Output Latch Threshold FAUXA/B Output Low Voltage FAUXA/B Output High Voltage FAUXA/B Output Latch Threshold
NOTES Specifications subject to change without notice.
Min 19 0.13 0.23 19 19 93 1.0 9.4 8.9 -
Typ 25.0 16 4.5 0.7 1 0.18 0.38 25 16 3 2.5 0.25 0.25 0.5 1.0 2.9 110 25.0 16 3 2.5 5.3 3 100 500 1.6 10 9.1 0.5
Max 29 1 1.3 0.25 0.52 29 5 TBD TBD TBD TBD TBD 29 8 TBD 107 960 2.1 10.2 9.3
Units A ms s
Test Conditions/Comments PWRON = High, V 12VG = 10V C12VG = 0.033F, 12VG Falling 90% - 10% C12VG = 0.033F, 12VG Rising 10% - 90% PWRON = High, ID = 0.1A, TA=TJ=25oC PWRON = High, ID = 0.1A, TA=TJ=70oC VOCSET = 0.6V VOCSET = 1.2V PWRON = High, VM12VG = -10V CM12VG = 0.033F, CM12VO= 50F,RL= 120 CM12VG=0.033F,M12VG Falling 90% -10% PWRON = High PAUXON = High, ID = 0.375A, TA=TJ=25oC PAUXON = High, ID = 0.375A, TA=TJ=70oC VOCSET = 0.6V VOCSET = 1.2V PAUXON = High, VAUXG = 3V CAUXG = 0.033F CAUXG = 0.033F, AUXG Rising 10% - 90% AUXIN Voltage Rising
A A A ms s mA
A A V ns A ms s V mA mA A ns V V V V V V V V V
12VINA Voltage Rising 12VINA Voltage Falling IFLT = 2mA IFLT = 0 IFLT High to Low transition IFAUX = 2mA IFAUX = 0 IFAUX High to Low transition
0.7 TBD 1.6 TBD 0.5 0.7 AUXIN-0.5 AUXIN-0.1 TBD 1.6 TBD
AUXIN-0.5 AUXIN-0.1
REV. PrN 1/02
-3-
ADM1014-SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise noted)
ORDERING GUIDE
Model ADM1014JRU Temperature Range 0C to +70C Package Description 38-Pin TSSOP Package Option RU-38
VCC , 12VIN . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V 12VO, 12VG, 3V5VG . . . . . . . . . . -0.5V to V 12VIN +0.5V -12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -14.0V to +0.5V -12VO, -12VG . . . . . . . . . . . . . . . . . . . V-12VIN -0.5V to +0.5V 3VISEN, 5VISEN . . . -0.5V to the Lesser of 12VIN or +7.0V Voltage, Any Other Pin . . . . . . . . . . . . . . . . . . -0.5V to +7.0V 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A -12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A Continuous Power Dissipation (TA = +70oC) . . . . . . 667mW TSSOP (derate 8.3mW/oC above +70oC) Operating Temperature Range Commercial (J Version) . . . . . . . . . . . . . . . . 0C to +70C Storage Temperature Range . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300C
*This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
PIN CONFIGURATION
M12VOA M12VGA PWRONA FLTNA FAUXA OCSET AUXGA AUXOA 12VGA 12VOA 12VOB 12VGB AUXOB AUXGB FAUXB FLTNB PWRONB M12VGB M12VOB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 M12VINA 37 3VISENA 36 3VSA 35 5VISENA 34 5VSA 33 3V5VGA 32 GND 31 AUXINA
ADM1014
TOP VIEW (Not to Scale)
30 PAUXONA 29 12VINA 28 12VINB 27 PAUXONB 26 AUXINB 25 3V5VGB 24 5VSB 23 5VISENB 22 3VSB 21 3VISENB 20 M12VINB
THERMAL CHARACTERISTICS
38-Pin TSSOP Package: qJA = 100C/Watt, qJC = 10C/Watt
-4-
REV. PrN 1/02
ADM1014
PIN FUNCTION DESCRIPTION
Pin 1 2
Mnemonic M12VOA M12VGA
Function Switched -12V output for channel A. Rated for 100mA. Gate of channel A internal NMOS transistor. A capacitor connected from this pin to -12VOA (pin 1) sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25A current source. Power on control for channel A. 3.3V CMOS-compatible logic input controls all four main supplies. PWRONA high = outputs on, PWRONA low = outputs off. Active-low, 5V compatible, Open Drain fault output for channel A. A pull-up resistor connects the pin to 3.3VAux. 4.7k is recommended for this function. An optional capacitor may be connected from this pin to GND to provide improved immunity to power supply transients. Active-low, 3.3V compatible, Open Drain fault output for Aux channel A. The same pull-up resistor as that on FLTNA connects the pin to 3.3VAux. Overcurrent set for all 10 outputs. A resistor connected from this pin to ground sets the overcurrent trip point of all eight supplies. All eight overcurrent trip-points can be programmed by changing the value of this resistor. The default value of 6.04k , 1% is compatible with the maximum currents allowed by the PCI specification. Gate of channel A +3.3VAUX internal PMOS transistor. A capacitor connected from this pin to AUXOA (pin 8) sets the start-up ramp for the +3.3VAUX supply. During turn-on, this capacitor is charged from a 25A current source. Switched 3.3V auxiliary output for channel A. Rated for 0.375A. Gate of channel A internal PMOS transistor. A capacitor connected from this pin to 12VOA (pin 10) sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25A current source. The undervoltage circuitry is disabled when the voltage on 12VGA rises above 1.2V. If the capacitor on pin 7 (AUXGA) or pin 33 (3V5VGA) is more than 25% larger than the capacitor on pin 9 (12VGA) a false undervoltage condition may be detected during startup. Switched 12V output for channel A. Rated for 0.5A. Switched 12V output for channel B. Rated for 0.5A. Gate of channel B internal PMOS transistor. A capacitor connected from this pin to 12VOB (pin 11) sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25A current source. The undervoltage circuitry is disabled when the voltage on 12VGB rises above 1.2V. If the capacitor on the pin 25 (3V5VGB) or pin 14 (AUXGB) is more than 25% larger than the capacitor on pin 12 (12VGB) a false undervoltage condition may be detected during startup. Switched 3.3V auxiliary output for channel B. Rated for 0.375A. Gate of channel B +3.3VAUX internal PMOS transistor. A capacitor connected from this pin to AUXOB (pin 13) sets the start-up ramp for the +3.3VAUX supply. During turn-on, this capacitor is charged from a 25A current source. Active-low, 3.3V compatible, Open Drain fault output for Aux channel B. The same pull-up resistor as that on FLTNA connects the pin to 3.3VAux. Active-low, 5V compatible, Open Drain fault output for channel B. A pull-up resistor connects the pin to 3.3VAux. 4.7k is recommended for this function. An optional capacitor may be connected from this pin to GND to provide improved immunity to power supply transients. Power on control for channel B. 3.3V CMOS-compatible logic input controls all four main supplies. PWRONB high = outputs on, PWRONB low = outputs off. Gate of channel B internal NMOS transistor. A capacitor connected from this pin to -12VOB (pin 19) sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25A current source. Switched -12V output for channel B. Rated for 100mA.
3 4
PWRONA FLTNA
5 6
FAUXA OCSET
7
AUXGA
8 9
AUXOA 12VGA
10 11 12
12VOA 12VOB 12VGB
13 14
AUXOB AUXGB
15 16
FAUXB FLTNB
17 18
PWRONB M12VGB
19
M12VOB
REV. PrN 1/02
-5-
ADM1014
PIN FUNCTION DESCRIPTION (CONTINUED)
Pin 20 21 22 23 24 25
Mnemonic M12VINB 3VISENB 3VSB 5VISENB 5VSB 3V5VGB
Function -12V supply input for channel B. Also provides power to the -12V overcurrent circuitry. 3.3V current sense for channel B. A current-sensing resistor is connected between this pin and 3VSB (pin 22). Connect to the load side of the current sense resistor. 3.3V source for channel B. The source of the 3.3V MOSFET is connected to this pin and a current-sensing resistor is connected between this pin and pin 21. 5V current sense for channel B. A current-sensing resistor is connected between this pin and 5VSB (pin 24). Connect to the load side of the current sense resistor. 5V source for channel B. The source of the 5V MOSFET is connected to this pin and a current-sensing resistor is connected between this pin and pin 23. 3.3V and 5V gate output for channel B, drives the gates of the external 3.3V and 5V MOSFETs. A capacitor connected from this pin to GND sets the start-up ramp for the 3.3V and 5V supplies. During turn-on, this capacitor is charged from a 25A current source. The undervoltage circuitry is disabled when the voltage on 3V5VGB falls below 12VIN-1.2V. +3.3V auxiliary supply input for channel B. Power on control for channel B +3.3V auxiliary output. 3.3V CMOS-compatible logic input. PAUXONB high = outputs on, PAUXONB low = outputs off. Switched +12V supply input for channel B. Switched +12V supply input for channel A and for OCSET and power-on RESET circuits. Power on control for channel A +3.3V auxiliary output. 3.3V CMOS-compatible logic input. PAUXONA high = outputs on, PAUXONA low = outputs off. +3.3V auxiliary supply input for channel A. Ground for all chip circuits. Connect to common of power supplies. 3.3V and 5V gate output for channel A, drives the gates of the external 3.3V and 5V MOSFETs. A capacitor connected from this pin to GND sets the start-up ramp for the 3.3V and 5V supplies. During turn-on, this capacitor is charged from a 25A current source. The undervoltage circuitry is disabled when the voltage on 3V5VGA falls below 12VIN-1.2V. 5V source for channel A. The source of the 5V MOSFET is connected to this pin and a current-sensing resistor is connected between this pin and pin 35. 5V current sense for channel A. A current-sensing resistor is connected between this pin and 5VSA (pin 34). Connect to the load side of the current sense resistor. 3.3V source for channel A. The source of the 3.3V MOSFET is connected to this pin and a current-sensing resistor is connected between this pin and pin 37. 3.3V current sense for channel A. A current-sensing resistor is connected between this pin and 3VSA (pin 36). Connect to the load side of the current sense resistor. -12V supply input for channel A. Also provides power to the -12V overcurrent circuitry.
26 27 28 29 30 31 32 33
AUXINB PAUXONB 12VINB 12VINA PAUXONA AUXINA GND 3V5VGA
34 35 36 37 38
5VSA 5VISENA 3VSA 3VISENA M12VINA
-6-
REV. PrN 1/02
ADM1014
FA U X
AUXG VC
C
VC
C
AUXIN
PAUXON
CURRENT TRACKING AND I-V CONVERTER
COMP
VOCSET/1.2
AUXO
COMP
4.6V
INHIBIT
COMP
2.9V
FLT
INHIBIT
COMP INHIBIT
10.8V
VOCSET/14.5
COMP
5VISEN
5VS
VCC
3V5VG
ZENER REFERENCE
COMP
3VISEN
VOCSET/11.5
VCC
COMMON TO BOTH CHANNELS
100A
3VS
12VG
VCC
12VIN
OCSET
VOCSET
VCC
12V IN POWER-ON RESET
LOW WHEN VCC < 10V
COMP
VOCSET/0.8
CURRENT TRACKING AND I-V CONVERTER
12VO
GND
-12VG
VCC
-12VIN
-12VIN
PWRON
CURRENT TRACKING AND I-V CONVERTER
COMP
VOCSET/3.3
VCC
-12VO
3V5VG
CIRCUIT OF ONE CHANNEL SHOWN, BOTH CHANNELS ARE IDENTICAL. RESET AND OCSET CIRCUITRY WITHIN DASHED LINE IS COMMEON TO BOTH CHANNELS
Figure 1. Simplified Schematic
REV. PrN 1/02
-7-
ADM1014
FUNCTIONAL DESCRIPTION VOLTAGE OUTPUTS
Note: The OCSET current source obtains its power supply from 12VINA.
INTERNAL CURRENT LIMIT
The ADM1014 consists of two independent, identical channels, A and B, each of which controls four main power supply voltages and an auxiliary voltage. As the channels are identical, the following description applies to either channel, except where otherwise stated. An on-chip PMOS transistor connected between 12VIN and 12VO switches the +12V supply at currents up to 1.5A, whilst an on-chip NMOS transistor connected between -12VIN and -12VO switches the -12V supply at currents up to 0.38A. The +3.3V and +5V supplies are switched by external, N-channel MOSFETs, whose gate drive is provided by the 3V5VG pins. Using suitable MOSFETs, singly or in parallel, currents of several amps may be switched with very low voltage drops. The four main power supplies may be switched on and off under control of the PWRON pin. The 3.3V auxiliary supply has an on-chip PMOS transistor, which can switch currents at up to 1A. This supply is controlled independently of the other four supplies by the PAUXON pin. All five supplies are protected against overcurrent and the four positive supplies are also protected against undervoltage.
EXTERNAL CURRENT LIMIT
The +3.3VAUX, +12V and -12V supplies have the power MOSFET switches on-chip. These devices are protected and overcurrent shutdown is provided by a completely self-contained current sensing system. The output current through the on-chip power MOSFET is tracked at a lower level by a second, smaller MOSFET. The current through this MOSFET is then converted to a voltage, which is compared to a reference voltage determined by RSET. In the case of the +12V and -12V outputs, if the current-sense voltage exceeds this reference voltage, the comparator output will go high, the fault latch will be set and all four main outputs and the auxiliary output will be turned off. Similarly in the case of the auxiliary output, if the currentsense voltage exceeds the reference voltage, the comparator output will go high, the fault latch will be set, FAUXN/FLTN will go low, and the auxiliary output and the four main outputs will turn off. The typical internal limiting currents may be calculated as follows: ILIMIT (+3.3VAUX) = VOCSET /1.2 = (10-4 ILIMIT (+12V) ILIMIT (-12V) Where: ILIMIT = current limit in Amps RSET is resistor from OCSET to GND in Due to tolerances in the current tracking FETs, the variations in the internal current limit are quite wide, typically 20% of the calculated value for the +12V supply and +35/-20% of the calculated value for the -12V supply.
CHOICE OF RSET AND RSENSE Using the above equations, RSET is chosen to set the required current limits for the +3.3VAUX, +12V and -12V supplies. Once RSET has been chosen, RSENSE3 and RSENSE5 can be chosen to set the current limits for the 3.3V and 5V outputs.
RSET)/1.2 VOCSET 10-4 RSET
= 1.25 = 1.25 = (10-4
The external power MOSFETs are protected and overcurrent shutdown is provided on the +3.3V and +5V supplies by external current-sense resistors and on-chip comparators. Current-sensing resistors are connected between the +5V output pin and the 5VISEN pin, and between the +3.3V output pin and the 3.3VISEN pin. The sense pins are connected to the inverting inputs of the current-limit comparator directly, while the voltage outputs are connected to the non-inverting inputs via a reference voltage proportional to the voltage on the OCSET pin. This voltage is VOCSET/14.5 in the case of the 5V output and VOCSET/11.5 in the case of the 3.3V output. These values were chosen so that the 3.3V and 5V sense resistors could both be 5m in PCI applications. When the voltage drop across the current-sensing resistor exceeds the reference voltage, the output of the comparator will go high, the fault latch will be set and all four main outputs and the auxiliary output on the channel will be turned off. The other main channel and auxiliary channel will remain on. The reference voltages for the current-limit comparators are set by connecting a resistor between the OCSET pin and GND. An on-chip, 100A current source generates a voltage across this resistor. The current limit may also be adjusted by the choice of current-sensing resistor. ILIMIT(3.3V) = VOCSET/(11.5 = (RSET ILIMIT(5V) Where: ILIMIT = current limit in Amps RSET is resistor from OCSET to GND in RSENSE is current-sense resistor in -8- = (RSET
-4
= VOCSET /3.3 RSET)/3.3
For PCI applications RSET should be 6.04k and the current sense resistors should both be 5m 1%. This will set the current limits to the maximum values for the PCI specification. For other applications, the following limits should be noted. 1. The minimum value of RSET is limited by the minimum voltage the current-limit comparators can reliably sense, which is determined by noise, comparator offset voltage and the overdrive required to switch the comparator. The reference voltage set by RSET should not be less than 33mV for the 5V output, which has the smallest reference voltage. The minimum recommended value for RSET is 6k , which gives a reference voltage of 35mV for the 5V output and 45mV for the 3.3V output. 2. The maximum value of RSET is limited by the junction temperature. This is determined by the power dissipated in the onchip MOSFETs, (which is dependent upon the current passed REV. PrN 1/02
RSENSE3) RSENSE3) RSENSE5) RSENSE5)
10 )/(11.5 10-4)/(14.5
= VOCSET/(14.5
ADM1014
by the devices and their on-resistance), the thermal resistance of the package (100oC/W), and the ambient temperature. The maximum on-resistance of the +3.3VAUX MOSFET is 0.65 , that of the +12V MOSFET is 0.35 and that of the - 12V MOSFET is 0.9 , so the power dissipation will be: PD = (0.65 Where: PD is power dissipation in Watts I is current in Amps Under normal operating conditions the maximum recommended value for RSET is 15k .
UNDERVOLTAGE SENSING
(I+3.3VAUX)2 + 0.35
(I+12V)2 + 0.9
(I-12V)2)
Figure 2. FLTN and 3V5VG Delay
TABLE 1. FLT AND 3V5VG DELAY VS. CFLT
Undervoltage sensing of the +3.3V, +5V, +12V and +3.3VAUX supplies is carried out by four voltage comparators. The supply voltages being monitoring are applied to the inverting inputs of these comparators, whilst reference voltages of 2.9V, 4.6V, 10.8V and 2.9V (derived from an on-chip zener reference) are applied to their non-inverting inputs. Should any of the output voltages fall below the corresponding reference voltage, the output of the comparator will go high, the fault latch will be set, turning off all the supplies (main and auxiliary) on that channel.
FLTN AND FAUXN OUTPUTS The FLTN and FAUXN outputs are active-low, 3.3V compatible, Open- Drain fault outputs. These outputs are shorted together and then connected to the 3.3VAux supply using a 4.7k pull-up resistors. Should an overcurrent or undervoltage event occur on one of the supplies, main or auxiliary, then the fault latch will be set, FLTA and FAUXA or FLTB and FAUXB will go low and all outputs on the faulting channel will be turned off. PROGRAMMABLE FAULT LATCH DELAY
CFLT OPEN 0.001F 0.01F 0.1F
tA 0.1s 0.44s 2.9s 28s
t2A 0.05s 0.22s 1.5s 14s
POWER CONTROL INPUTS
The PWRONA and PWRONB inputs are 3.3V CMOS-compatible logic inputs, which may be used to switch all four main outputs on and off, and is also used to reset the fault latch and turn the outputs back on after an overcurrent or undervoltage shutdown. When PWRON is high, the four main supplies are turned on. With PWRON held low, the supplies are turned off. After an overcurrent or undervoltage shutdown, PWRON should be toggled low then high again to reset the fault latch and turn on the outputs. PAUXONA and PAUXONB are also 3.3V CMOS-compatible logic inputs which perform a similar function for the +3.3V auxiliary supplies.
POWER-ON SEQUENCE AND SOFT START
The delay between an overcurrent or undervoltage fault occurring and the outputs shutting down may be set by connecting a capacitor between a FLTN or FAUXN output and GND. This delays the start of the FLTN/FAUXN output 1 to 0 transition and slows down the fall time of the FLTN/FAUXN output, thus delaying shutdown of the outputs. If the fault latch threshold (~1.6V) is reached on FLTN/FAUXN then the fault latch will be set and the four supply outputs and the auxiliary output will be shut down. If the fault disappears before the latching threshold is reached, the fault latch will not be set and the FLTN/FAUXN output will return to a high state. This adjustable delay allows the ADM1014 to ignore overcurrent and undervoltage transients that might otherwise cause an unwanted shutdown. It should be noted that if a fault is asserted on FLTN and FAUXN at the same time, then the delay is halved, as shown in fig. 2 and Table 1.
When the device is powered on with PWRON held high, the outputs are inhibited by the power-on reset circuit and will not become active until VCC exceeds 10V. During this time the undervoltage comparators are inhibited and the fault latch is held in a reset condition. Note: the power-on reset circuit monitors 12VINA. After the power-on delay, all five outputs are turned on simultaneously. The undervoltage comparators are enabled when the voltage on the gate of the internal PMOS transistor, 12VG, has fallen below about 400mV. The rise time of the outputs may be controlled by connecting capacitors between the gate and output pins of the +3.3VAUX, +12V and -12V outputs, and from the 3V5VG pin to GND. During output turn-on, these capacitors are charged from a nominal 25A current source. Limiting the output rise times also limits the charging currents drawn by any supply decoupling capacitors in the circuits being driven. With fast turn-on these currents might be excessive and cause overcurrent faults at power-on. Care must be taken when choosing these capacitors. If the capacitor on AUXG or 3V5VG is more than 25% larger than
REV. PrN 1/02
-9-
ADM1014
the capacitor on 12VG, the +3.3VAUX, 3.3V and 5V outputs may not have exceeded their undervoltage thresholds by the time the undervoltage comparators are enabled, and a false undervoltage condition may be detected. For this reason it is recommended to use the same value for all three gate capacitors. For PCI applications the minimum recommended value is 0.033F. Smaller values may cause overcurrent faults at powerup due to excessive charging currents drawn by decoupling capacitors. The maximum value of the gate capacitors is determined by the need to discharge them quickly when turning off the outputs under fault conditions. If the capacitors are too large the ADM1014 may be unable to protect the power bus or the external MOSFETs. With 0.033F capacitors, the turn-off time will be less than 6s.
APPLICATIONS INFORMATION APPLICATION CIRCUIT
Figure 3 shows a typical circuit configuration for the ADM1014 in a PCI application, controlling supply voltages of +3.3V at up to 7.6A, +5V at up to 5A, +12V at up to 0.5A and -12V at up to 0.1A. In this circuit, two external MOSFETs are connected in parallel for the 3.3V and 5V outputs to minimise on-resistance.
12V -12V +3.3Vaux
SLOT 1
AUXINA AUXGA
5V
3.3V
C1 AUXOA
M12VINA M12GA 5VISENA
R1
5VSA 3V5VGA
C2
M12VOA M12VINB M12GB M12VOB 12VINA 12VGA 12VOA
+12V BUS -12V BUS
Q1
3V5VGB
C3
Q2
5VSB
R2
5VISENB
3.3V BUS
+3.3Vaux BUS
C4
ADM1014
3VISENA
R3
3VSA
C5
12VINB 12VGB 12VOB
Q3
Q4
3VSB
FROM SYSTEM CONTROLLER
AUXINB AUXGB C6 AUXOB
R4
3VISENB
C7
C8
PAUXONA
PWRONA
PWRONB PAUXONB
FLTNA
FAUXA FLTNB
FAUXB
OCSET GND R5
R11
C9
C10
C11
C12
R12
TO SYSTEM CONTROLLER
12V -12V +3.3Vaux
SLOT 2
Figure 3. Typical Application Circuit
3.3V
5V
-10-
REV. PrN 1/02
5V BUS
ADM1014
RL1
25 0m A
+12V C1
RL2
50m A
-12V C2
R L3
37 5m A
3.3Vaux C3 GND
RL4
2A
5.0V C4
R L5
3A
3.3V C5
Figure 4. Load Board for Typical Application Circuit
Main Board Components Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Qty 1 1 4 4 4 2 2 2 8 4 3 1 8 2 4 1 1 4 1 4 2 Ref Des U1 SKT1 Q1-4 D1-4 R1-4 R5-6 R7-8 R9-10 C1-8 C9-12 C13-15 S1 T1-8 P1-2 J1 J4-J6 J2 J3 P4-7 PCB R11-12 Load Board Description ADM1014 38 Pin Tssop Socket IRF7413 Power Mosfet Green SMD LED 5m Metal Strip Resistor 470 0805 chip resistor 1K5 0805 chip resistor 6K04 0805 chip resistor CAP,0.033UF CAP,0.47UF Electrolytic capacitor space SPDT Slide Switch Testpoint 20 Pin Edge Conn Skt 4mm 10A PCB Sockets-Red 4mm 10A PCB Sockets-Green 4mm 10A PCB Sockets-Black SMB EVAL-ADM1014 Main Board 4K7 0805 chip resistor Fully Assembled Load Board
Load Board Components Item 1 2 3 4 5 6 7 8 Qty 1 3 2 1 1 1 1 1 Ref Des PCB CL1-CL3 CL4-CL5 RL1 RL2 RL3 RL4 RL5 Description EVAL-ADM1014Load Board 100uF 16V Electrolytic Caps 2200uF 16V Electrolytic Caps 47 6W (W22 Series) Res 240 2.5W (W21 Series) Res 10 6W (W22 Series) Res 2.2 12W (W24 Series) Res 1 12W (W24 Series) Res
REV. PrN 1/02
-11-
ADM1014
LAYOUT CONSIDERATIONS
Any circuits supplied by the ADM1014 are outside the control loops of the main system power supplies, which means that any series resistance between the four supply inputs and the outputs will cause a degradation of the supply load regulation. This includes connector contact resistance, PCB trace resistance, onresistance of MOSFETs (both external and on-chip) and current sense resistors. Care must therefore be taken to ensure that: a) PCB traces are as heavy as possible. b)External MOSFETs have low-on resistance. c) Current sense resistors are as small as possible. The current sense resistors have very small values (5m in the preceding example) to minimise the voltage drop across them. Because of this, PCB trace resistance can be a significant percentage of the sense resistance. It is therefore essential to ensure that the ADM1014 senses the voltage drop directly across the sense resistors and not across any current-carrying trace resistance in series with them. Connections from the ADM1014 to the sense resistors must go directly to the ends of the resistors. Figure 4 shows examples of good and bad practice
CURRENT SENSE RESISTORS 35 34 37 VSENSE 36
22 21
24 VSENSE 23 34
ADM1014
CORRECT
CURRENT SENSE RESISTORS 21 35 34 37 VSENSE 36 ADDITIONAL VOLTAGE DROP
ADDITIONAL VOLTAGE DROP
ADDITIONAL VOLTAGE DROP 22 21 24 VSENSE 23 ADDITIONAL VOLTAGE DROP ADM1014
INCORRECT
Figure 4. Good and Bad Practice For Sense Resistor Connection
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
38-Pin TSSOP (RU-38)
0.386 (9.80) 0.378 (9.60)
38
20
0.177 (4.50) 0.169 (4.30)
0.256 (6.50) 0.246 (6.25)
1 19
PIN 1
0.006 (0.15) 0.002 (0.05)
0.0433 (1.10) MAX
SEATING PLANE
0.0200 (0.50) 0.0106 (0.27) BSC 0.0067 (0.17)
0.0079 (0.20) 0.0035 (0.090)
88 08
0.028 (0.70) 0.020 (0.50)
-12-
REV. PrN 1/02

▲Up To Search▲

Price & Availability of ADM1014

	To Download ADM1014 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .